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December 18, 2007

Mtg: Panel Discussion – Best of ISTFA

by @ 2:09 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Optics/Displays, Semiconductors

WEDNESDAY January 23
SCV Reliability Chapter
Organizer: Art Rawers
Time: Refreshments at 6:30 PM, Presentation at 7:00 PM,
Cost: none
Place: Hewlett Packard Oak Room, Bldg 48 (Just North of Hwy 280, Wolfe Rd Exit), Cupertino
RSVP: not required, but email if you are interested in being on the panel or contributing


The International Symposium for Testing and Failure Analysis (ISTFA) provides a forum for the latest developments in wafer, chip, package, and board level test and failure analysis. The 30th ISTFA was held November 4-8, 2007, in San Jose. Information on ISTFA is available on the web at The January Santa Clara Valley IEEE Reliability Society meeting will feature a panel discussion of selected papers from ISTFA. The panel is being organized by Art Rawers. We are looking for additional panel members, especially ISTFA attendees. If you are interested in helping select papers, being on the panel, leading a discussion, or contributing in another way, please e-mail us at


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