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October 28, 2010

Mtg: Photoprinting Assembly Technology for Ultrathin Electronic Components

by @ 7:25 pm. Filed under ALL, BioEngineering, Communications, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors

WEDNESDAY December 8, 2010
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Dr. Jayna Sheats, Terepac Corporation
Time: Networking and buffet dinner at 6:00 PM; Presentation at 6:45 PM
Cost: $20; $10 for fulltime students and currently unemployed; $5 more at door
Place: Biltmore Hotel, 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara
RSVP: from website, by Dec. 6

Packaging continues to push toward smaller and thinner assemblies to accommodate the demands of mobile consumer products.? 3D integration provides another driver for the use of ultrathin components.? The wireless sensors market, envisioned by many to be in the trillions, requires microprocessors with tens of thousands of transistors and memory in the kilobyte range.? These devices need to be very inexpensive and typically, flexible and small.
We have developed an assembly and packaging technology which can effectively handle electronic components of almost any useful size, down to the micron scale in both thickness and lateral size.? ? ? Interconnections are printed from soluble precursors, allowing for much smaller I/O pad periods than solder bumping or wirebonding.? Flexibility is achieved without any compromise in electrical performance compared to conventional packaging.
The ability to package ultrathin components rests on a process in which parts are transferred from diced wafer directly to a รข??printing plate???, and then released by the action of light and heat on a photoactive polymer.? Thus the complex mechanical action of the pick and place process is replaced by photoprinting, requiring much simpler mechanics with increased throughput.? While our emphasis has been on low part count products such as smart cards and simple wireless sensors, the technique can also handle larger (cm-scale) dice, and could provide an alternative for stacking bare die in wafer level packages.

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