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December 30, 2007

Mtg: Silicon Technology Scaling and ESD Challenges

by @ 12:24 pm. Filed under ALL, Electronics Design, NanoEngineering, Semiconductors
 

MONDAY January 14
SCV Electron Devices Chapter
Speaker: Dr. Charvaka Duvvury, Texas Instruments
Time: Refreshments at at 6:00 PM, Presentation at 6:15 PM
Cost: none
Place: National Semiconductor Corp. Building E-1 – Auditorium CMA, 2900 Semiconductor Drive, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

 

The trends in silicon technology scaling towards the sub-100 nm range, along with the introduction of newer transistor structures such as the multi-gate and Fin-FET devices, are driving sensitive issues for ESD development and IC protection design.? This is compounded by the complex interactions from aggressive circuit design improvements that include high speed applications, 3.3V and 5V analog functions in 90nm and 65nm technologies, and other mixed voltage applications.? Even more complex is the System-on-Chip (SoC) that integrates RF, Analog and Digital functions on the same chip, and more recently the stacked die and stacked package approaches.? This presentation will first examine the advances in transistor structures and their impact on intrinsic ESD robustness. ? This will be followed by a summary of the issues related to the new effects of IC packages.? Finally, the ESD technology road map and the practical methods that should be followed to maintain ESD reliability into the next decade will be offered.? ? ?

 

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