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December 30, 2007

Mtg: IC Chips – from Scaling to Emerging Nanotechnology

by @ 12:26 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

TUESDAY January 22
SCV Electron Devices Chapter
Speaker: Dr. Bin Yu, NASA Ames Research Center
Time: Refreshments at at 6:00 PM, Presentation at 6:15 PM
Cost: none
Place: National Semiconductor Corp. Building E-1 – Auditorium CMA, 2900 Semiconductor Drive, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

 

It is predicted that silicon CMOS FET could be ultimately scaled down to 1.5 nm gate length based on the least energy model for computing. ? However, it is anticipated that a gate length of 4~5 nm would be the practical limit (in mass production around year-2020). ? In this seminar, some major trends will be discussed of the mainstream IC chip technology in the next 1½-decade towards the â??scaling-end??? of ITRS Roadmap. ? There are technology candidates that are of strategic importance beyond the Roadmap. ? Some were actively explored in research community for long, while a few others were catching up rapidly.

â??Bottom-up??? approach, the core concept of nanotechnology, is to employ inexpensive chemistry to promote self-assembly of mesoscopic architectures. ? Nanostructures offer unique properties such as energy efficiency, surface sensitivity, self-assembly, low material/processing cost, etc., that could be the valuable building blocks for the next-generation electronic chips. ? In this seminar, we discuss some potential â??successors??? of the concurrent silicon chip technology at the end of Semiconductor Roadmap. ? These disruptive technologies are rooted in nanoscale materials or structures -synthesized by inexpensive chemistry – which exhibit exceptional materials and electrical properties. ? The new technologies would help continued advancement, not necessary through straightforward geometry scaling, of solid-state chip technology in applications such as information processing and nonvolatile data storage. The state-of-the-art research in the front will be introduced. Major challenges and future directions will be also discussed.

 

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