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March 3, 2011

Mtg: The Different Faces of Variability in IC Manufacturing

by @ 1:19 pm. Filed under ALL, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

THURSDAY March 24, 2011
SCV Solid State Circuits Chapter
Speaker: Dr. Marcel Pelgrom, Philips Research Laboratories, The Netherlands
Time: Presentation at 6:00 PM
Cost: none
Place: National Semiconductor Building E Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: from website
Web: ewh.ieee.org/r6/scv/ssc

Circuit design greatly depends on the ability to control and reproduce transistor and process parameters. Variation in processing was in the past countered by defining process corners: boundaries in parameter variation that accounted for process tolerances. With the improved control over processing, this batch-to-batch variation is largely under control.
However, now an additional class of phenomena has appeared: statistical variations. These variation between otherwise identical components is generally described by รข??mis-match??? parameters. Some analog ICs with differential operation (e.g. analog-to-digital converters) were already affected by mismatch. In advanced
technologies every circuit from SRAM cell to an I-Q mixer is affected by statistical variations.
Next to these static random phenomena also time-dependent variations play an increasingly important role: variations in supply voltage and temperature and interference (supply and substrate noise, cross-talk, etc.) are of major importance to optimize circuit performance. Understanding and mitigating these effects requires more and more statistical means.
This talk will review some of the statistical effects and discuss the various techniques that analog designers in the past used to mitigate statistical issues. Lessons from the analog domain can provide a starting point for the application in the digital domain.

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