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March 12, 2011

Mtg: Physical Verification Challenges and Solutions for 45nm and Beyond

by @ 12:57 pm. Filed under ALL, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

MONDAY May 16, 2011
SCV Circuits and Systems Chapter
Speaker: Haifang Liao, Celesda Design Solutions Inc.
Time: Networking/Light Dinner at 6:30 PM; Presentation at 7:00 PM
Cost: $2 donation for food
Place: QualComm, Building B, 3165 Kifer Road, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/cas

Advanced semiconductor technology provides the capability to integrate billions of transistors for SOC designs, the tape-out data for manufacture reaches terabyte magnitude, and the complexity of design rules in the deep sub-wavelength processes increases explosively.? This talk will review challenges of physical verification for complicated SOC designs on 45nm process and beyond.? We analyze properties of various applications in different aspects, complexity of design rules and layout structures, and introduce a fast platform for physical verification as well as design-for-manufacture (DFM) to analyze, verify, modify and optimize designs.? The new solution is fully compatible with the existing design flow and offers multiple times speed up with signoff quality.

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