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March 20, 2011

Mtg: Next-Generation Wireless Communication Systems

by @ 6:52 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt
 

MONDAY March 21, 2011
SCV Circuits and Systems, with Communications Chapter
Speaker: Yoshikazu Miyanaga, Hokkaido University
Time: Networking/Light Dinner at 6:30 PM; Presentation at 7:00 PM
Cost: $2 donation accepted for food
Place: QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara
RSVP: not required
Web: ewh.ieee.org/r6/scv/cas

Currently, sophisticated wireless technologies, such as digital broadcasting, wireless LAN and wireless PAN, have enabled high-speed data transmission in home and personal networks. The IEEE802.11a-based wireless LAN supports a maximum of 54 Mbps at a 20-MHz frequency band by using orthogonal frequency division multiplexing (OFDM).
As the next wireless LAN system, the Enhanced Wireless Consortium (EWC) proposal set a goal to achieve the maximum of 600 Mbps using a multiple-input and multiple-out (MIMO) stream technique with OFDM. The EWC proposal was to be adopted in the IEEE802.11n standard. The standardization of IEEE802.11n was concluded in 2009. There are four main modifications from the IEEE802.11a standard, i.e., a 40-MHz baseband bandwidth, a 400-ns short guard interval, 5/6 coding rate and a 4×4 MIMO scheme. A new study group of IEEE802.11, i.e., IEEE 802.11ac, started last year and they would like to develop â??Over Giga Bit??? Wireless Networks. In this talk, a system â??over 1G??? bps throughput, â??over 80MHz??? bandwidth and â??less than 6GHz??? carrier is introduced.
We had the goal of achieving a data rate of 600 Mbps by use of an 80-MHz baseband bandwidth and a 2×2 MIMO scheme several years ago. This system occupies a double bandwidth compared with IEEE 802.11n. If we apply a 4×4 MIMO scheme for the next system, we can design a 1.2G bps wireless communication system.
This talk describes the VLSI implementation of our proposed 4×4 MIMO-OFDM (2.6G bps with 160MHz BW) and 8×8 MIMO-OFDM systems. A low-latency and a full-pipelined architecture are employed for all processing blocks to provide real-time operations on OFDM modulation and MIMO detection. The designed transceiver has been evaluated for circuit size and power dissipation by using a 90-nm CMOS process. In an FPGA board, the proposed total system has been implemented. For the designed system, the circuit behavior, gate size and power consumption has been verified. The communication performance is also evaluated.

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