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April 7, 2011

Mtg: Future ESD Challenges for IC Components and Systems

by @ 12:50 pm. Filed under ALL, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors

THURSDAY April 14, 2011
SCV Electron Devices Chapter
Speaker: Charvaka Duvvury, Texas Instruments (Dallas), EDS Distinguished Lecturer
Time: Presentation at 2:00 – 4:00 PM
Cost: none (bring quarters for metered visitor parking)
Place: Stanford University, Paul G. Allen Building Annex, Auditorium 101, 420 Via Palou Mall, Stanford
RSVP: not required

Component level IC protection against ESD has seriously become a major challenge due to advanced scaling of silicon technologies and the development of complex high speed circuits including the effects of system on chip (SoC) applications. Analog and RF designs pose particular limitations. Simultaneous to these, the IC package technology roadmap for larger high pin count packages and the System in Package (SiP) are making it more complicated to design the expected component level ESD performance while meeting the IO high speed requirements. In addition to the necessary component level ESD protection for safe handling at the IC production areas, the system level ESD protection at the board level during end-user applications is becoming even more critical. An understanding of coupling from the interface pins and cross-coupling between pins of different ICs on the board would be important for system level ESD protection designs. This seminar will address these important topics and give an insight into the strategies for coupling from component to system protection design. A roadmap for ESD and the need for innovative approaches that include advanced simulations will be reviewed.

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