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April 11, 2011

Mtg: Spin Torque MRAM Technology: Physics, Design, and Implementation Challenges

by @ 3:50 pm. Filed under ALL, Computers/Software, Electronics Design, NanoEngineering, Semiconductors

TUESDAY April 19, 2011
SCV MagneticsChapter
Speaker: Robert Beach, PhD., MagIC Technologies, Inc.
Time: Conversation & Pizza at 7:00 PM; Presentation at 7:30 PM
Cost: none
Place: Western Digital, 1710 Automation Parkway, San Jose
RSVP: not required

This talk will present the physics of Spin-Torque Transfer Magneto-Resistive RAM (STT-MRAM) in magnetic tunnel-junctions. It becomes difficult to scale down the bit cell for conventional field-based MRAM beyond the 90nm node, and the industry is keen to bring STT-MRAM into advanced products. A tutorial presentation of the physics behind tunneling magnetoresistance (TMR) and STT will be followed by a consideration of various STT design options for the MRAM bit. These include the recent discovery of perpendicular magnetic anisotropy in thin CoFeB films adjacent to MgO, and the design of the TMR stack and physical bit dimensions for optimal electrical and magnetic performance. Of paramount importance to the realization of a STT memory is a careful study of array statistics. Bits in the STT-MRAM array need to be engineered so they can be written and read repeatedly and reliably under multiple write cycles, down to the PPM level. Control of the distributions that determine these attributes is critical for STT-MRAM to be successful in the marketplace.

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