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April 23, 2011

Mtg: 3D IC Development and Supply Chain Collaboration

by @ 7:41 am. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors

THURSDAY April 28, 2011
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Suresh Ramalingam, Ph.D., Senior Director Advanced Package Design & Development, Xilinx Inc.
Time: Registration at 11:30 AM; Buffet lunch at 11:45; Presentation (no cost) at 12:15 PM
Cost: $15 ($5 for full-time students, unemployed). $5 more at door
Place: Biltmore Hotel, 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara
RSVP: from website

Driven by the ever-increasing internet bandwidth needs, 2.5D/3D packaging with TSV has gained a lot of attention, interest and momentum.? Significant increases in interconnection density, lower latency and improvement in Bandwidth-per-watt makes this technology attractive.? Starting with high-end CMOS image sensors and high-power applications, the technology looks to penetrate high-performance FPGA, graphics and mobile applications.
In October 2010, Xilinx announced the Stacked Silicon Interconnect Technology that produces a new class of high-capacity, resource-rich FPGAs.? These 28nm-based FPGA products are slated to go into production in early 2012.? As the role of the FPGA becomes more dominant in system design, the designs grow larger and more complex, demanding higher logic capacity and more on-chip resources.? To date, FPGAs have depended predominantly on Mooreâ??s Law to respond to this need, delivering nearly twice the logic capacity with each new process generation.? However, keeping pace with todayâ??s high-end market demands requires more than Mooreâ??s Law increases can provide.
This new packaging offers bandwidth and capacity one full generation ahead of when they otherwise become available using traditional Mooreâ??s law scaling.? By combining through-silicon via (TSV) and micro-bump technology with its innovative ASMBLâ?¢ architecture, Xilinx is building a new class of FPGAs that delivers the capacity, performance, capabilities, and power characteristics required to address the programmable imperative.? Xilinx stacked silicon interconnect technology combines enhanced FPGA die slices and a passive silicon interposer to create a die stack that implements tens of thousands of die-to-die connections to provide ultra-high inter-die interconnect bandwidth with far lower power consumption and 1/5th the latency of standard I/Os.
Technology development, supply chain and platform scalability were key focus areas to bring Stacked Silicon Interconnect Technology to fruition.? Industry infrastructure development is in its early days with some IDMs, foundries and OSATs leading the way.? Significant investment is required to enable the TSV, thin wafer handling, backside process and micro-bump assembly.? Key technology challenges such as TSV Cu protrusion, KGD/PGD strategy, microbump yield and reliability, package reliability and thin wafer processing need to be understood and resolved.? On the supply chain side the process flow and hand-off between foundry and OSAT is tricky, requiring careful technical and business assessment.? This presentation will cover some aspects of Stacked Silicon Interconnect Technology and Supply Chain collaboration model.

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