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August 24, 2011

Mtg: Metal Interconnects for Large-area Power Devices: Physics, Challenges, and Solutions

by @ 4:30 pm. Filed under ALL, Electronics Design, NanoEngineering, Semiconductors

TUESDAY September 13, 2011
SCV Electron Devices, with Nanotechnology Chapter
Speaker: Dr. Maxim Ershov, CTO, Silicon Frontline Technologies
Time: Networking and pizza at 6:00 PM; Presentation at 6:15 PM
Cost: none
Place: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara
RSVP: not required

Layouts of multi-layer metallization of large-area power semiconductor devices have a profound effect on device performance and reliability.? Metals, vias, and contacts used to route the currents and voltages for source and drain nets impact the metal debiasing, device on-resistance (Rdson), current crowding and current spreading, and uniformity of the current distribution over the area of the device.? However, the design, analysis, and optimization of the metal layouts is often driven by rules of thumb, or by the experimental trial and error method, which is very time consuming, costly, and error-prone.? Things are further complicated by multiple and frequently changing design rules and constraints related to both on-chip (metal interconnects) and off-chip (leadframe, package, and PCB) requirements.? The lack or scarcity of literature on the subject (both textbooks and research publications) makes the problem much worse, especially for non-expert designers and engineers.? In this talk, we will review the basic principles of metal layout design for power devices, analyze the underlying physical effects, and highlight typical mistakes.? We will also discuss the “best practices” drawn from the analysis, simulation, and optimization of many real design examples.? Finally, we will show how using a dedicated simulation software can help to get an insight into the physics of metal interconnects and to guide design optimization.

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