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September 17, 2011

Mtg: Memory Scaling and Its Potential Impact on Computing and Storage

by @ 8:24 am. Filed under ALL, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

THURSDAY September 22, 2011
SCV Components, Packaging and Manufacturing Technology, with Circuits & Systems, Computer, and Electron Devices Chapters
Speaker: Ed Doller, VP and Chief Memory Systems Architect, Micron Technology
Time: Registration at 11:30 AM; Buffet lunch at 11:45 AM; Presentation at 12:15 PM
Cost: $15 if reserved by Sept 20; $5 for fulltime students and currently unemployed; $5 more at door
Place: Biltmore Hotel, 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara
RSVP: from website
Info: www.cpmt.org/scv/meetings/cpmt1109l.html

As memory technologies scale current memory, usage models will be challenged.? While new emerging technologies hold promise to solve the scalability challenge, it is unlikely that they will be “drop in compatible” with current technologies and thus will impact current memory hierarchies and utilization in the compute and storage segments.? At the same time, lines are beginning to blur both in the compute segment and the storage segment as the debate over direct-attached storage is heating up รข??- again.? Ed Doller, VP of Micron’s architecture research and development team, will explore the impact of scalability on current memory technologies, discuss what technologies may be next, and assess the impact of both of these on computer and storage architectures and on packaging options.

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