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October 24, 2011

Mtg: Reliability and Yield of MOS Devices and Circuits

by @ 6:48 am. Filed under ALL, Electronics Design, NanoEngineering, Semiconductors
 

WEDNESDAY November 9, 2011
SCV Circuits and Systems Chapter
Speaker: Prof. Gilson Wirth, Universidade Federal do Rio Grande do Sul
Time: Networking and light dinner at 6:30 PM; Presentation at 7:00 PM
Cost: $2 accepted for food
Place: QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/cas

With the device sizes shrinking well below 100 nm and introduction of novel materials in the fabrication technology, new phenomena started playing a role on the reliability of MOS devices. As a consequence, performance and reliability become influenced also by factors other than physical dimensions. We need to understand the underlying physical mechanisms, and develop analysis and modeling techniques to support IC designers. Furthermore, the variations of parameters over time (aging and transient effects such as noise and soft errors) may lead to dramatically increased overhead in the timing budget, as well as on test procedures.
Effects that play a major role on the reliability of today digital and analog designs are discussed, as well as effects that are expected to become relevant in future technologies.
Modeling techniques to abstract the physical level effects into the design flow are studied.
Among the effects discussed, the major ones are:
– Parametric variability due to effects such as random dopant fluctuations and line edge roughness.
– Aging effects such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), Electromigration and Time Dependent Dielectric Breakdown (TDDB).
– Radiation Effects as Single Event Transients (SET) and Single Event Upsets (SEU).
– Device intrinsic noise, with focus on the Random Telegraph Signal (RTS). Besides its importance for analog design, as a source of low-frequency noise, RTS is also becoming a concern in digital circuits, as for instance in SRAM and flash memories. RTS may be modeled as momentary changes in threshold voltage, meaning that circuit behavior may change between two logic operations of a digital circuit. Different modeling approaches are discussed, focusing on operation conditions relevant for digital and analog design, including large signal AC operation.
Design techniques to improve yield and reliability are also addressed.
Mutual relation between the different reliability phenomena is also studied. For instance, charge trapping and de-trapping plays a role in both bias temperature instability and low-frequency noise, and random dopant fluctuations may exacerbate the impact of BTI and noise on circuit performance.

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