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January 6, 2012

Mtg: Next-Generation 100 Gigabit Ethernet, Low-Power CMOS SerDes, and Signal Integrity Challenges

by @ 9:45 am. Filed under ALL, Communications, Electronics Design, Semiconductors
 

WEDNESDAY February 15, 2012
SCV Circuits and Systems Chapter
Speaker: Hamid Rategh, Inphi
Time: Networking/Light Dinner at 6:30 PM; Presentation at 7:00 PM
Cost: $2 donation accepted for food
Place: QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara
RSVP: not required
Web: ewh.ieee.org/r6/scv/cas

The continued rapid growth in multimedia and mobile traffic over the Internet is driving service providers and datacenter operators to adopt next-generation 100 Gigabit Ethernet (100GbE) technology based upon IEEE 802.3ba 100GbE-LR4/ER4 standards.? To meet this bandwidth demand, the industry must innovate to achieve high speed, low power, small form factor, and low cost that has been the hallmark of Ethernet technologies.? We will discuss a new 100GbE architecture based upon low-power CMOS SerDes technology and some of the challenges from the signal integrity point of view to meet the higher bandwidth, lower power, higher port density, and lower cost requirements of such systems.

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