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May 24, 2012

Mtg: Scaling-friendly Radio Design for SoC

by @ 5:41 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

THURSDAY June 21, 2012
SCV Solid State Circuits Chapter
Speaker: Yorgos Palaskas, Intel Labs, Hillsboro
Time: Presentation at 6:00 PM
Cost: none
Place: Texas Instruments Building E Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: From the website
Web: sites.ieee.org/scv-sscs

Integration of RF together with baseband and possibly application processors in a System-on-Chip is appealing for cost and form-factor reasons.? Conventional radios are generally incompatible with SoC: they require accurate RF models (which prevents quick SoC porting to the next process node), and they might not scale with CMOS process, e.g. due to the lowering supply voltage, inductors not getting smaller, etc.? Scaling-friendly radios, on the other hand, introduce fundamentally different ways to encode the information that alleviates these issues.? For example, the information can be encoded in the phase of the signal, rather than the amplitude, resulting in improving resolution and performance with CMOS scaling.? Furthermore, these circuits now operate in switching mode and can be adequately described with a basic digital MOS model (hence no need for RF models), and certain RF blocks might be possible to implement with digital Auto-Place-and-Route, which would further improve time-to-market.? Advanced DSP and digital calibration integrate seamlessly in these systems and can further enhance the performance.? The talk will present case studies demonstrating the potential of such scaling-friendly radio concepts.? For example, a digital 32nm WiFi transmitter will be presented where OFDM modulation is introduced by means of high resolution (1.4ps), digital delay cells.? The transmitter includes a switching, inverter-based 26dBm power amplifier that was designed with no RF models and still closely matched design targets.? The presented scaling-friendly radio systems achieve compelling performance already in 32nm CMOS and are expected to further improve with further CMOS scaling, almost on par with digital circuits.

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