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July 24, 2012

IEEE Tutorial on LDPC Decoding: VLSI Architectures and Implementations

by @ 5:20 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, Semiconductors
 

WEDNESDAY August 22, 2012
SCV Professional Activities Committee for Engineers (PACE)
Speakers: Ned Varnica, Marvell Semiconductor; Kiran Gunnam, NVIDIA
Time: 7:00 PM – 9:30 PM
Cost: none
Place: Santa Clara Convention Center, Santa Clara
RSVP: from website (requires no-cost Exhibits registration for Flash Summit)
Web: sites.ieee.org/scv-pace

LDPC is now being used in Hard disk drive read channels, Wireless (IEEE 802.11n/ IEEE 802.11ac, IEEE 802.16e WiMax), 10-GB, DVB-S2, and more recently in Flash SSD.? This tutorialâ??s target audience is systems engineers and design engineers. The tutorial has two parts, with the first module focused on LDPC Decoding and the second module focused on VLSI Architectures and Implementations.

Module 1 LDPC Decoding
1.1) LDPC codes
1.2) Hard decision decoding,
1.3) LLR basics and LLR generation for soft decoding for Flash memory channel
1.4) Soft decoding and Min-Sum Algorithm
1.5) Code Construction Methods
1.6) Code performance characteristics, better error floor and efficient hardware.

Module 2 VLSI Architectures and Implementations
2.1) Check Node Unit Design and Value-reuse property
2.2) Non-layered decoder architecture
a) Block serial processing
b) Translating throughput requirement to H matrix parameters and edge parallelization
2.3) Layered decoder architecture
a) Block serial processing
b) Block serial processing for irregular H matrices, scheduling of decoder processing
c) Block parallel processing
d) Translating throughput requirement to H matrix parameters and edge parallelization
e) Case study of decoders for 802.11n and Flash channel

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