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September 24, 2012

Mtg: Accelerating Analog Design

by @ 8:35 am. Filed under ALL, Electronics Design, Engineering Mgmt, Semiconductors
 

THURSDAY October 18, 2012
SCV Solid State Circuits Chapter
Speaker: S. S. Mohan, Synopsys
Time: Networking with pizza at 6:00 PM; Presentation at 6:30 PM
Cost: none
Place: TI Auditorium E, 2900 Semiconductor Drive, Santa Clara
RSVP: from website
Web: sites.ieee.org/scv-sscs

We investigate state-of-the art technology that accelerates analog design by automatically custom sizing an architecture to satisfy specifications for a chosen process over process, voltage and temperature (PVT) variations.? The talk begins with an overview of manual and automated circuit design methods and identifies the iterative and time-intensive steps that result in the analog bottleneck.? We then describe how an equation-based optimizer and optimization friendly process-models are combined with a unified system and circuit formulation that is independent of specification and process to enable analog/RF circuits to be designed and ported efficiently while also documenting the operation of the circuit.? Then, innovations and ease-of-use features that address difficulties associated with traditional equation based optimization methods are presented.? The talk concludes with illustrative applications of commercial equation-based optimization tools in ADC, PLL, RF LCO, opamp, regulator and Serdes designs to highlight how this compelling methodology is leveraged for? process and corner aware, simultaneous optimization of system and circuit across different levels of hierarchy and abstraction.

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