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November 8, 2012

Mtg: New Class of Low-k Dielectrics for Advanced Interconnects

by @ 8:54 am. Filed under ALL, Electronics Design, NanoEngineering, Semiconductors
 

WEDNESDAY January 9, 2013
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Yusuke Matsuda, Materials Science and Engineering, Stanford University
Time: Optional dinner at 6:00 PM; Presentation at 6:45 PM
Cost: $20 for dinner ($10 for students, unemployed); no cost for presentation
Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa Clara
RSVP: from website
Web: www.cpmt.org/scv

Low-k dielectrics in microelectronic interconnects play a crucial role in increasing device performance and lowering power consumption.? Silica-based low-k dielectrics are fragile, and have low device yield in packaging and limited reliability from cohesive or interfacial fracture caused by thermo-mechanical and packaging stresses in the interconnect structures.? This is further aggravated in reactive environments like moisture or CMP slurries.? These issues may be addressed by replacing Si-O-Si bonds with less reactive molecular networks to dramatically increase device reliability.
Here, I present new silicon carbide-based low-k dielectrics containing no Si-O-Si bonds.? These can be processed using available techniques, and exhibit excellent and widely tunable thermo-mechanical properties, as well as significant reduction of moisture-assisted cracking.? These dielectrics can replace traditional silica-based low-k dielectrics in advanced interconnects, leading to a better damage tolerance, increased reliability and yield during packaging, chip stacking and TSVs processes.

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