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December 11, 2012

Mtg: New Wafer-Level Embedded Package Structure and Technology using Large-Scale Panel Assembly

by @ 5:16 pm. Filed under ALL, Electronics Design, Semiconductors

THURSDAY February 21, 2013
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Akio Katsumata, General Manager, J-Devices Corporation
Time: Registration at 11:30 AM; Buffet lunch at 11:45; Presentation at 12:15 PM
Cost: $15 for lunch ($5 for students, unemployed); no cost for presentation
Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa Clara
RSVP: from website

This presentation describes a new embedded package structure and technology for the next generation of WLP, the Wafer level Fan-Out Package – WFOPâ?¢.? A face-down mounting style, the WFOP has a metal stainless steel or copper plate as a basis for the redistribution interconnection layer.? The redistributed layer is fabricated with a semi-additive copper plating method.? The contact between the die pads and distribution layer is the lead-finger type.
With this structure we reduce fabrication costs by using large-scale panels and precise redistribution interconnect controls, and the design rules do not depend on the die size.? Moreover, WFOP has several benefits:
– applicable to 50um pad pitch;
– excellent thermal characteristics contributed by the metal plate; and
– noise shielding afforded by the metal plate.
Reliability testing has been completed.
In this presentation, we describe the WFOP package structure, process flow, package characteristics and reliability test results and discussion.

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