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January 30, 2013

Mtg: Towards Storage Class Memory: 3-D Crosspoint Access Devices using Mixed-Ionic-Electronic-Conduction (MIEC)

by @ 12:23 pm. Filed under ALL, Computers/Software, Electronics Design, NanoEngineering, Semiconductors

TUESDAY February 12, 2013
SCV Electron Devices Chapter
Speaker: Dr. Geoffrey W. Burr, IBM Almaden Research Center
Time: Networkingand pizza at 6:00 PM; Presentation at 6:15 PM
Cost: none
Place: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr., Santa Clara
RSVP: not required

Memory technology is currently going through a period of rapid change, as new non-volatile memories (NVM) emerge that complement, augment, (and potentially could even replace) the traditional triad of SRAM, DRAM, and Flash.? Storage-class memory (SCM) is an emerging memory category that seeks to combine the benefits of solid-state memory, such as high performance and robustness, with the long-term retention and low cost of conventional hard-disk magnetic storage.? ? In fact, the potential exists for two entirely new and distinct levels within the memory and storage hierarchy, termed M-SCM and S-SCM, located within the large gap in access times between off-chip DRAM and NAND Flash.
However, such SCM technologies will require large nonvolatile memory arrays that can be manufactured at a very low cost per bit.? One path to this goal is to stack multiple layers of NVM crosspoint arrays in 3D. In such an architecture, the NVM element at each crosspoint intersection must be in series with an access device, whose strong nonlinearity makes it possible to drive high current density through selected cells while maintaining ultra-low leakage through unselected cells.? 3D stacking is only possible if both the NVM and the access device are fully compatible with a Back-End-Of-the-Line (BEOL) fabrication process.
This talk will provide both an overview of the Storage Class Memory concept and a review of our work on novel access devices based on Cu-containing Mixed-Ionic-Electronic-Conduction (MIEC) materials.? Our MIEC-based access devices not only meet all of the above requirements but also support the bipolar memory operation critical for NVM candidates such as Resistance RAM (RRAM) and Spin-Torque-Transfer Magnetic RAM (STT-MRAM). Extensive experimental results on prototype MIEC devices will be shown, addressing topics such as cycling endurance, array fabrication and yield, integration with Phase Change Memory (PCM), speed, and scalability.

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