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May 13, 2013

Mtg: Wafer Level Packaging: A Foundry Perspective

by @ 9:01 am. Filed under ALL, Electronics Design, Semiconductors
 

THURSDAY June 27, 2013
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Michael Shillinger, Founder, Innovative Micro Technology
Time: Registration at 11:30 AM; Buffet lunch served at 11:45 AM; presentation (no cost) at 12:15.
Cost: $15 for lunch ($5 for students, unemployed); no cost for presentation
Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa Clara
RSVP: from website
Web: www.cpmt.org/scv

Wafer Level Packaging (WLP) and customized electrical I/O schemes have become mature technology platforms within the MEMS industry. The needs for these technologies were dictated by the sensitive nature of MEMS devices in the ambient environment. This presentation will discuss design, process and testing considerations of both WLP and electrical I/Os.

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