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June 19, 2013

Mtg: Electrical Signaling at 64Gb/s/Lane

by @ 8:29 am. Filed under ALL, Communications, Electronics Design, Semiconductors
 

THURSDAY June 20, 2013
SCV Solid State Circuits Chapter
Speaker: Dr. Elad Alon, UC Berkeley
Time: Networking and snacks at 6:00 PM; Presentation at 6:30 PM.
Cost: none
Place: Texas Instruments Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: from website
Web: sites.ieee.org/scv-sscs

The demand for I/O bandwidth in modern SoCs continues to grow at an exponential rate, forcing the per-lane bandwidth of electrical links to rise at a tremendous pace.  While there have been several demonstrations of electrical I/O operating at ~40Gb/s/lane to date, achieving these data-rates has so far come at the cost of substantial penalty in energy-efficiency vs. optimized lower-rate designs.
In this talk I will describe our on-going work in pushing the data-rate of electrical links to 64Gb/s and beyond.  I will begin by describing a proposed active connector topology as well as the methodology we used to elucidate the feasibility of links operating at this rate over ~1m of cable interconnect.  I will next move on to describe our first experimental demonstration of a critical component within such a link â?? specifically, a multi-tap decision feedback equalizer.  Through a series of design optimizations that I will describe in the talk, this closed-loop, 3-tap design achieves 66Gb/s error-free operation over 1e13 bits with only 46mW of power consumption in a standard 65nm CMOS process.

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