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June 25, 2013

Tutorial on LDPC Decoding, VLSI Architectures and Implementations

by @ 2:45 pm. Filed under ALL, Communications, Electronics Design, Semiconductors

WEDNESDAY August 14, 2013
SCV PACE (Professional Activities Committee for Engineers)
Speakers: Dr. Ned Varnica, Marvell Semiconductor; Dr. Kiran Gunnam, NVIDIA
Time: 7:00 PM to 9:30 PM
Cost: $30
Place: Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara
RSVP: from website

LDPC codes are now being used in Hard disk drive read channels, Wireless (IEEE 802.11n/ IEEE 802.11ac, IEEE 802.16e WiMax), 10-GB, DVB-S2, and more recently in Flash SSD.  Tutorialâ??s target audience is system engineers and design engineers.  Tutorial has two parts, first module is focused on LDPC Decoding and second module is focused on VLSI Architectures and Implementations.

Module 1: LDPC Decoding
1.1) LDPC codes
1.2) Hard decision decoding,
1.3) LLR basics and LLR generation for soft decoding for Flash memory channel
1.4) Soft decoding and Min-Sum Algorithm
1.5) LDPC decoder performance characteristics, trapping sets and error floor
1.6) Basics of Code Structures for Efficient hardware.

Module 2: VLSI Architectures and Implementations
2.1) Check Node Unit Design and Value-reuse property
2.2)   Non-layered decoder architecture
a)   Block serial processing
b)  Translating throughput requirement to H matrix parameters and edge parallelization
2.3)  Layered decoder architecture
a) Block serial processing
b) Block serial processing for irregular H matrices, scheduling of decoder processing
c) Block parallel processing
d) Translating throughput requirement to H matrix parameters and edge parallelization
e) Case study of decoders for 802.11n and Flash channel
2.4) Error floor mitigation schemes

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