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July 29, 2013

Mtg: Semiconducting Nanowire Arrays Grown Directly on Graphene: Towards Precision Placement of Wafer Scale Nanowire Arrays with Improved Electrical Contact for Energy Storage and Harvesting

by @ 12:00 pm. Filed under ALL, Electrical/Power, NanoEngineering, Semiconductors
 

WEDNESDAY September 11, 2013
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: John Alper, PhD Candidate, UC-Berkeley
Time: Optional dinner at 6:00 PM; Presentation at 6:45 PM
Cost: $20; $10 for full-time students and unemployed ($5 more at door)
Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa Clara
RSVP: from website
Web: www.cpmt.org/scv/meetings/cpmt1309.html

Semiconducting nanowires (NWs) have been demonstrated as promising in a number of devices due to novel properties which are intrinsic to their nanoscale. Silicon NW geometry allows for relaxation of mechanical stress associated with lithium insertion, potentially avoiding the rapid degradation observed in silicon Li-ion battery electrodes. They are also attractive for thin-film solar cells, where the NW array geometry results in enhanced broadband absorption and enables thinner cells with increased efficiency. As well as silicon, the properties of silicon carbide NWs including large specific surface area and high aspect ratio lend them to application as supercapacitor electrodes and field emitters respectively. In the fields of energy harvesting and storage, semiconducting NWs have the potential to be game-changers at both the micro and macro scale.
Typically these NW arrays are grown via vapor deposition techniques at high temperatures (800 – 1000 ºC) in corrosive atmospheres (e.g. hydrochloric acid vapor). These growth conditions require refractory, rigid and chemically inert growth substrates which are less than ideal as active components for many of the devices mentioned above. Thus in order to integrate NW arrays they must be accurately transferred to the desired location and electrically contacted. Previous efforts in the transfer step have utilized the Langmuir-Blodgett technique or polymer stamping. Such transfer schemes suffer from increased complexity due to the number of steps. As well polymer stamping methods increase the potential for contamination of the NW surfaces, which can be detrimental to performance. After the transfer, electrical contact is then typically made through metal evaporation which involves wasted materials, high energy requirements and masking to avoid deposition in undesired areas of the device. In this talk a greatly improved process flow for growth, transfer and contact of NW arrays will be described. The process begins with growth substrate choice — graphene on sacrificial oxide. Graphene, a highly conductive, flexible, and mechanically robust substrate acts as both the electrical contact and mechanical support for the NWs during transfer from the sacrificial oxide to desired substrate. This reduces processing steps, potential for contamination, wasted materials, and energy costs for the manufacture of NW integrated devices.
The discussion will focus on describing the materials process flow and the potential benefits of the process in terms of ease of integration and enhanced performance for energy harvesting and storage. In addition results from the structural characterization of the NW-graphene hybrids will be shared. Silicon carbide nanowireââ?¬â??graphene hybrid supercapacitor electrode performance studies, indicating good electrical contact throughout the array and robust lifetime cycling behavior, will also be presented as a device proof of concept.

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