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August 8, 2013

Mtg: Low-CTE Organic Interposer Technology for 2.5D Packaging

by @ 5:55 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Semiconductors
 

THURSDAY September 26, 2013
SCV Components, Packaging and Manufacturing Technology
Speaker: Tomoyuki Yamada, Kyocera America Inc.
Time: Buffet lunch at 11:30 AM; Presentation at 12:15 PM
Cost: $15; $5 for full-time students and unemployed ($5 more at door)
Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa Clara
RSVP: from website
Web: www.cpmt.org/scv/meetings/cpmt1309l.html

In recent years, a 2.5D package has been developed to accommodate high-speed data processing and miniaturization in microelectronics. In the industry, most of the development work has been implemented with silicon interposer technology, which was fabricated with legacy wafer manufacturing equipment.  This is because of the excellent ground rules available for silicon and the lower Coefficient of Thermal Expansion (CTE) when compared to organic substrate technology.
The body size for 2.5D packages has been increasing, which is driven by the number of logic and memory chips per interposer as well as their footprints.  Due to the body size limitation of silicon interposers, there is a significant industry need for a large organic interposer to support high-performance 2.5D packages, and potentially 3D packages.
This presentation describes the development of a low-CTE organic Chip Scale Package (CSP) for 2.5D packaging.  The new material set, identified as “Advanced SLC Package”, combines a low-CTE core with build-up dielectric materials to achieve a composite laminate CTE of 9-12 ppm/oC, which is between that of silicon devices and conventional PCBs.  The composite CTE reduces the dimensional mismatch between chip and laminate during Bond and Assembly (BA) to mitigate Chip-Package Interactions (CPI).  The low CTE significantly reduces the strain in the solder joints during the reflow process and ensures solder joint reliability.  In addition, the CTE mismatch of device solder interconnect pads between the silicon chip and laminate during device attach is less pronounced during the C4 joint cooling-down period.  In this presentation, the design rules will be examined based upon the new low-CTE organic material parameters as well as the CSP form factor.  Mechanical and electrical characterizations were conducted and models were developed and verified.  This presentation will also highlight potential CSP applications for 2.5D packages including next generation high-performance memory technologies, such as Wide I/O Memory and High Bandwidth Memory.  Lastly, the technology roadmap for organic interposers will be discussed in order to support future 2.5D packaging.

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