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August 14, 2013

Half-day: Power Electronics: Below the Silicon Limit

by @ 8:55 am. Filed under ALL, Communications, Electronics Design, NanoEngineering, Semiconductors
 

FRIDAY September 6, 2013
SCV Electron Devices Chapter seminar
Speakers: Deva Pattanayak, Senior Director, Vishay Siliconix; Dan Kinzer, CTO, Fairchild; Alex Lidow, CEO, EPC; Dave Anderson, Chief Technologist and GM, Kilby Labs Silicon Valley, Johan Strydom, Applications Engineering, EPC
Time: 12:30 PM to 5:00 PM
Cost: $30 for IEEE members, $60 for non-members ($15 for student members, $30 for student non-members)
Place: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr., Santa Clara
RSVP: from website
Web: www.ewh.ieee.org/r6/scv/eds
Power electronics is re-emerging as an important and innovative area.  This is due to the increasing importance of electricity in our lives, and the need to use it more efficiently.  The old paradigm involved large inductors and capacitors, slow silicon devices, and a barrier known as the â??silicon limitâ?.  The new revolution is fueled not only by improved Si device technology using conductivity and field-modulation, but also by exciting new materials such as GaN and SiC that have taken devices beyond the silicon limit.  Designers are making use of this substantially improved performance to increase efficiency and reduce size.  This half-day symposium has presentations from leading contributors in the multidisciplinary field of power electronics.  Topics include Si, SiC and GaN device technology, the bottlenecks to power switching, and power electronics applications.  It will be of significant interest to both device and circuit engineers, or students and experts, who wish to develop a broader perspective and increase their depth and breadth of knowledge.

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