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April 8, 2008

Mtg: High Performance Modules on Copper Substrates:Next Generation Packaging for Servers and Supercomputers

by @ 7:37 am. Filed under ALL, Communications, Computers/Software, Electronics Design, Semiconductors
 

WEDNESDAY May 14
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Peter Salmon, VP, Salmon Technologies, LLC
Time: Seated dinner at 6:30 PM, Presentation (no cost) at 7:30 PM
Cost: $25 for dinner
Place: Ramada Inn, 1217 Wildwood Ave (Fwy 101 frontage road, near Lawrence Expy), Sunnyvale
RSVP: by email to Janis Karklins, karklins@ieee.org
Web: www.cpmt.org/scv

 

A concept for a high-performance module using build-up layers on copper is presented. Copper provides mechanical support, an electrical backplane, good thermal conductivity, and is impervious to water. Photolithographic processing can be performed on wafer-sized copper substrates using coaters and aligners (from Suss Microtec, for example). Stacked module configurations can be well-cooled, and have good test and rework capabilities.

The ability to make compact assemblies with high silicon content spurs parallel development in the areas of cooling, testing, and rework. New test and cooling concepts will be described, looking towards automated assembly, test, and rework at the wafer level. Potential innovations in socketing and optical interfaces will also be briefly described.

The packaging strategies are supported by 12 new patent applications, some of which have issued.

 

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