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November 10, 2013

Mtg: Design, Manufacturing and Performance of a 3D Random Access Memory Subsystem

by @ 3:59 pm. Filed under ALL, Computers/Software, Electronics Design, Semiconductors

WEDNESDAY November 13, 2013
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: David Chapman, VP Technical Sales and Marketing, Tezzaron Semiconductor, Inc.
Time: Optional dinner at 6:00 PM; Presentation at 6:45 PM
Cost: $20; $10 for full-time students and unemployed ($5 more at door)
Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa Clara
RSVP: from website

The litany of problems associated with 3D ICs is long and ugly.  Early adherents have been taking it on the chin for poor yields, high costs, impossibly difficult process steps, questionable reliability and up to now, relatively little gain for all their pain. 3D has been a technology-in-waiting for a decade.  But despite excruciatingly slow progress towards volume manufacturing, a broad conviction that it ought to work and should produce amazing results has persisted.
This talk will cover the architecture and the manufacturing flow used to build a 3D random access 64Gb volatile memory subsystem that produces 4Tb/s of data bandwidth, with 7ns random access latency.  This 3D implementation solves the problems with 3D and enables the production of ICs with outstanding yield and that pass thermo-mechanical tests with ease.  Specific enabling technologies such as tungsten vias, DBITM wafer bonding and self-test and repair will described.  Performance characteristics including power consumption will be presented.


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