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April 19, 2008

Mtg: Implementation of a Third Generation 16-Core 32-Thread Chip-Multithreading SPARC Processor

by @ 8:15 am. Filed under ALL, Computers/Software, Electronics Design, Semiconductors
 

MONDAY April 21
SCV Circuits and Systems Chapter
Speaker: Georgios K. Konstadinidis, SUN Microsystems
Time: Fast food and drinks at 6:30 PM; Presentation at 7:00 PM
Cost: none
Place: Cadence Design Systems, Building 5, 655 Seely Avenue, San Jose
RSVP: not required
Web: ewh.ieee.org/r6/scv/cas

This third-generation Chip-Multithreading (CMT) SPARC processor consists of 16-cores with shared memory architecture and supports a total of 32 main Threads plus 32 Scout Threads. ? It is targeted for high-performance servers, and is optimized for both single- and multi-threaded applications. ? The 396mm2 chip, is fabricated in a 11M 65nm CMOS process and operates at a nominal frequency of 2.3GHz, consuming a maximum power of 250W at 1.2V. ? This presentation provides a brief overview of the Architectural highlights followed by a more in-depth discussion on the physical implementation aspects of this design. ? The focus is on the physical implementation challenges and solutions, including circuit innovations in memory arrays, register files, and floating-point hardware that boost the performance and circuit robustness with low area overhead.

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