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April 24, 2008

Mtg: An 802.11n 2×2 MIMO Radio in 0.13um CMOS (and) A Bluetooth v2.1 radio in 0.13um CMOS

by @ 2:34 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors

SCV Solid State Circuits Chapter
Speakers: Dave Weber and Sotirios Limotyrakis, Atheros Communications, Inc
Time: Refreshments at 6:00 PM; Presentation at 6:30 PM
Cost: small donation for food
Place: National Semiconductor, Building E, Auditorium, 2900 Semiconductor Dr, Santa Clara
RSVP: not required


An 802.11n-draft-compliant 2×2 2-stream MIMO radio SoC incorporates two dual-band RF transceivers, analog baseband filters, data converters, digital PHY and MAC, and a PCI Express interface. Implemented in a 0.13-um CMOS, it occupies 36mm2. For 2.4GHz/5GHz, the receive chain NF is 4dB/6dB, and the transmit EVM is -34dB/
-30dB at -5dBm output power. Details will be presented on the RF and baseband sections of the chip.

A single-chip Bluetooth v2.1-compliant CMOS radio SoC that supports Enhanced Data Rates is implemented in standard 0.13-um CMOS technology. Radio architectures have been chosen that minimize the area of the analog and RF circuits. This design features a polar transmitter, a two-point modulated fractional-N synthesizer, a 500kHz IF receiver with first order low-pass analog filtering, and a delta-sigma ADC. The total SoC die area is 9.2mm2 with only 3.0mm2 used for analog and RF circuits. The basic-rate radio power consumption is 28mA in receive and 30mA in transmit.


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