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January 27, 2014

Mtg: Product-Level Reliability Challenges Originating from TDDB, BTI and Variability

by @ 3:17 pm. Filed under ALL, Engineering Mgmt, NanoEngineering, Semiconductors

TUESDAY February 18, 2014
SCV Electron Devices Chapter
– scaling, degradation mechanisms, correlation …
Speaker: Dr. Tanya Nigam, GlobalFoundries
Time: Networking and pizza at 6:00 PM; Presentation at 6:15 PM
Cost: none
Place: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr., Santa Clara
RSVP: not required

As we continue scaling towards 10 nm, reliability is becoming an integral part of the complete technology offering.  Building in reliability is critical to the success of future scaling.  For sub-100 nm technologies, material changes have been necessary to meet the power, performance and reliability requirements.  In the sub-45 nm regime, SiOx based dielectrics have been replaced by HK MG leading to new degradation mechanisms such as PBTI and also changed the understanding of existing mechanisms such as TDDB.  As we scale further we need to comprehend interaction between device-level variability pre- and post-stress and circuit functionality.  In this talk I will address some of the challenges and correlation of device level reliability learning to simple circuits such ring oscillator and SRAM cells.  Also I will outline the efforts being made to extend these to product level solutions.


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