IEEE S.F. Bay Area Council e-GRID's
BayAreaTech

WEDNESDAY April 9, 2014
SCV Components, Packaging and Manufacturing Technology Chapter
– new solutions, transition, current designs …
Speaker: Herb Reiter, eda2asic Consulting, Inc.
Time: Networking and buffet dinner at 6:00 PM; Presentation (no cost) at 6:45 PM
Cost: $20; $10 for full-time students and unemployed ($5 more at door)
Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa Clara
RSVP: from website
Web: www.cpmt.org/scv/meetings/cpmt1404.html

Continued shrinking of logic circuits — Moore’s Law — is getting technically more and more difficult and extremely costly.  Many applications require logic as well as integration of memory, analog/RF, MEMS, sensors and other functions.  Package-on-Package (PoP), System-in-Package (SiP) and other such solutions have been developed, but can’t meet current and projected system requirements for speed and power.  New solutions such as 2.5D [IC dice placed side by side on an interposer], and 3D [multiple IC die stacked vertically within one package] seem to be the Holy Grail that everyone is after.
In part 1 (from 7 to 8 PM) of this presentation Mr. Reiter will outline the reasons for this ongoing transition to 2.5/3D-ICs, highlighting their features and benefits. He will discuss design and manufacturing changes needed to meet the economic and manufacturing challenges. Some examples of designs currently in production, in prototype-evaluation, and planned designs will be presented.
In part 2 (starting about 8 PM), based on an on-site survey of topics of interest, specific areas of interest to the audience will be discussed in greater depth.