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February 27, 2014

Mtg: Digital-Analog Design Tools: Challenges and Trends

by @ 3:23 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Semiconductors
 

THURSDAY April 17, 2014
SCV Solid State Circuits Chapter
– implementations, models, validation, process variations …
Speaker: Mark Horowitz, Stanford University
Time: Presentation at 6:30 PM
Cost: none
Place: Texas Instruments Building E Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: from website
Web: sites.ieee.org/scv-sscs

The past 30 years have seen an enormous growth in the power and sophistication of digital design tools, while progress in analog tools has been much more modest.  Digital tools use many abstractions to allow them to validate implementations match the functional models, and the composition of cells matches the composition of the functional models.  While there are many reasons why this is more difficult for analog circuits, it can be done.  To prove this point, this talk presents how to leverage the fact that the result surface of analog designs are smooth to create ways to formally validate analog models to instances, define analog fault models, and even efficiently explore the effect of process variations.

20140417scv

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