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March 24, 2014

Mtg: System Level On-Chip ESD Protection

by @ 2:52 pm. Filed under ALL, Electronics Design, Engineering Mgmt, Semiconductors
 

THURSDAY April 15, 2014
SCV Electron Devices Chapter
– high current, parasitics, waveforms, latchup, tests …
Speaker: Dr. Vladislav Vashchenko, Maxim Integrated Corp.
Time: Networking and pizza at 6:00 PM; Presentation at 6:15 PM
Cost: none
Place: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr., Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

A significant paradigm shift in systems and analog IC design has been initiated by new market demands over last decade.  Integration of emerging technologies, increases in data rate, rapid evolution of portable and mobile devices, lower power consumption and operating voltages, dramatic increase of electronic content in automotive products with 0ppm failure rate target and substantial progress in medical applications have created demand for on-chip protection against system level ESD and surge stresses.  This has impacted ESD specifications for analog ICs, has changed understanding of the system standards and test methodologies that now applied to the component level, as well as initiated intensive R&D for a broad range of aspects from new high-current-capable ESD on-chip devices up to advanced Si TVS components with extremely low parasitic capacitance and precise waveforms.  Thus a new on-chip system-level protection ESD design culture has emerged and is evolving further.  It involves not only the physical design of high current capable on-chip devices, but requires us to take into account both high voltage and transient latchup phenomena, board and system blocks design with off-chip components as well as understanding of the correlation factors for the devices, pulse types and test setups.  This trend is ramping up toward creation of a new system-IC co-design approach.  The talk presents a structural physical understanding of the major aspects involved in the modern system level on-chip ESD design.  The talk is organized in five sections that combine (i) introductory material for major principles and methodologies of the system level ESD design, (ii) quintessence of ESD and surge test standards and methods both for on-chip and board level with TVS protection; (iii) describes the essentials of the device and clamp level solutions for on-chip system level ESD protection, further extended toward (iv) the remaining aspects of the IC design, latchup and transient-induced latchup, and finally concluded by (v) outlining the chip-system co-design approach.

20140415scv

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