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May 14, 2014

Mtg: Inkjet Printing for Advanced Semiconductor Packaging, & Improved PoP Package Competes with 2.5/3D Packages using TSVs

by @ 2:22 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

WEDNESDAY June 11, 2014
SCV Components, Packaging and Manufacturing Technology Chapter
– materials, nanoparticles, die stacking, process, yield …
Speakers: Jake Sadie, Ph.D. Candidate, EECS, UC-Berkeley; and Dev Gupta, PhD, CTO, APSTL LLC
Time: Networking and buffet dinner at 6:00 PM; Presentation (no cost) at 6:45 PM
Cost: $30; $25 for IEEE members; $10 for full-time students and unemployed ($5 more at door)
Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa Clara
RSVP: from website
Web: www.cpmt.org/scv/meetings/cpmt1405.html

As integrated circuits continue to scale and interest in new, thin form factors continues to grow, electrical interconnects and back-end-of-line (BEOL) packaging technologies are becoming an increasingly critical factor in overall chip performance. Improving material performance, implementing chip stacking, and decreasing overall costs are three primary drivers for next-generation packaging schemes, and inkjet printing of metal nanopartices is uniquely positioned to deliver on all three fronts. Due to their high surface area-to-volume ratio, encapsulated metal nanoparticles exhibit dramatically reduced melting points, enabling low-temperature sintering processes that result in high-conductivity structures. However, most nanoparticle-based fabrication has been confined to two-dimensional thin films rather than three-dimensional structures relevant to the packaging industry. To this end, we explore the necessary processing conditions and ultimate structural properties of two three-dimensional, nanoparticle-based structures: pillars and through-silicon vias (TSVs).
In the first talk, we will first explore inkjet printing processes for the fabrication of three-dimensional structures using gold nanoparticles and demonstrate the key process parameters required for freestanding pillar fabrication and TSV filling. Next, we consider the sinter-dependent material properties (electrical, elastic, and shear) for pillars and TSVs. Using heat treatments which do not exceed conventional BEOL process temperatures, it is possible to achieve printed structures with properties that outperform conventional packaging materials and approach bulk gold properties. We use custom four-point probe techniques, nanoindentation, solder bump shear testing, and focused ion beam with a goal of understanding the sintering processes for our inherently thick-film, nanoparticle-based structures. Finally, we discuss manufacturability of this process with respect to uniformity, yield, and the inherent systems constraints imposed by inkjet-driven processes.
Talk B:
The industry has been awaiting maturation of 3D packaging technologies as a low-cost alternative to further integration. So far die stacking and interconnecting with Through Silicon Vias (TSVs) have received most attention.  The adoption of 3D TSVs for manufacturing has been limited to cases where its use has resulted in performance benefits and reduced costs, e,g. BSI modules used in some Smart Phones.  Cost reduction (by reduced yield losses) has been a key factor in the adoption of 2.5D for small-scale production of high-end FPGAs built as a multi-chip module rather than a single large chip.  Such cost reduction has not yet been possible for CPU-Memory combinations in 3D stacks.
This is not simply because of the high initial cost or supply-chain issues typical of new technologies, but also due to unresolved issues related to choice of material and process flow for 3D TSVs.  These concerns, along with stress and thermal issues that affect device performance in 3D stacks, will be discussed.
Lower-risk alternatives that can be implemented even in consumer systems e.g. Smart Phones are evaluated. To identify “low hanging fruit” analyses was carried out to simulate bandwidth and power needed to transfer data in 3D stacks and 2.5D modules using TSVs as well as several packages that do not use TSVs for application to Smart Phones.
PoP (poor man’s 3D) are ubiquitous in Smart Phones. APSTL project to improve electrical performance e,g. power efficiency (battery life) and bandwidth (video rate) of PoP packages will be described.  Improved performance of the resulting Super PoP will be discussed and contrasted with other industry efforts to improve the PoP package.

20140611scv

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