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August 13, 2014

IEEE Mtg: The “Invisible” IC Package

by @ 1:56 pm. Filed under ALL, Electronics Design, Semiconductors

THURSDAY September 25, 2014
SCV Components, Packaging and Manufacturing Technology Chapter
– chip-package-PCB design, form-factor, thermal, SI, cost …
Speaker: Sam Karikalan, Senior Manager of Package Engineering, Broadcom Corporation
Time: Networking and buffet lunch at 11:30 AM; Presentation (no cost) at 12:15 PM
Cost: $25 for IEEE Members, $30 for non-members, $10 for studens/unemployed
Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa Clara
RSVP: from website

The never-ending demand for improved electrical performance and cost reduction in IC packages has spawned many Chip-Package-PCB co-design innovations in the industry.  On the one end, need for higher memory bandwidth and die-level cost reduction are driving high-end packaging technology and infrastructure development.  On the other end, emerging markets such as Wearables and Internet of Things are adding more form-factor and cost pressures on the more conventional packaging technologies.  Architectural-level changes and innovative Signal Integrity and Thermal solutions are needed to keep packaging performance impact and cost under control, in all such cases.  Increasing I/O count in high-end applications has also enabled the development of new materials for use in large-body-size packages.  This presentation will discuss some of the die, package and system-level design measures that are becoming common in the industry to help make the traditional IC package more and more ‘invisible’, from both performance and cost viewpoints.


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