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December 2, 2014

Mtg: Tools for Thermal Analysis: Thermal Test Chips

by @ 8:12 am. Filed under ALL, Electronics Design, Semiconductors

Wednesday December 10, 2014
SCV Components, Packaging and Manufacturing Technology Chapter, with the MEMS & Sensors Chapter
– chip/package/heatsink, sensing, gradients, unit-cells, package design …
Speaker: Tom Tarter, Package Science Services LLC
Time: Networking and optional dinner at 6:00 PM; Presentation at 6:45 PM
Cost: $25 for IEEE Members, $33 for non-members, $10 for fulltime students and currently unemployed (no cost for talk)
Place: Biltmore Hotel, 2151 Laurelwood Rd, Santa Clara
RSVP: from website

Irrespective of if a device gets smaller, larger, hotter or cooler, some method is needed to determine the thermal behavior of a given chip/package/heatsink configuration. This is typically achieved by a combination of models and measurements and is useful in guiding the design team to the most cost-effective and reliable package and cooling solution. Most production chips have few or no available connections for temperature sensing and require complex biasing schemes and clock signals to achieve maximum power dissipation. Although some live devices may be evaluated for thermal performance, there is no clear indication of the on-chip temperature distribution. As we shrink feature size and combine more functions onto a given chip, the problem of temperature distribution becomes critical. Now, and as we move into more integrated chip functionality, temperature gradients and ‘hot spots’ must be considered to evaluate thermal performance and reliability. Another scenario that is difficult or impossible using live die is to determine the junction temperature of chips in various locations in a multi-chip application. In stacked, SiP, 2.5 and 3D packaging, the problem also includes measuring temperatures across the stack or array of chips. These factors, among others, can make using production die for thermal test expensive, inconclusive, or impossible.
The alternative is to use specially designed thermal test chips. These chips make available power dissipating elements and temperature sensors in unit-cells, arrayable into various chip sizes. Sensors are addressable for each unit-cell on the array and resistor elements may be combined in various circuit configuratons to allow power variation anywhere in the array. Very high power density can be achieved in these die, limited only by interconnect current density and maximum temperature. Power supply and sensor reading does not require switching and allows simple connection and data collection. This chip set is a valuable tool in the modern design arsenal.
The talk will focus on specifications and applications of the thermal test chip with examples to illustrate how the chip can be used to select and optimize cooling options, package design, cost, and time-to-market.


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