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July 23, 2008

Mtg: Power and Leakage Reduction in the Nanoscale Era

by @ 4:23 pm. Filed under ALL, Electronics Design, NanoEngineering, Optics/Displays, Semiconductors
 

THURSDAY August 21, 2008
SCV Solid State Circuits Chapter
Speaker: Stefan Rusu, Senior Principal Engineer, Intel Corp.
Time: Refreshments at 6:00 PM; Presentation at 6:30 PM
Cost: small donation for food
Place: National Semiconductor Building E, Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/ssc

To continue harvesting technology scaling benefits, it is essential for chip designers to understand the nature and impact of active power and leakage, its sensitivity to different design parameters, and practical techniques to reduce it. ? This talk will review design techniques for active power and leakage management with examples from recent industry designs and academic research.

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