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July 14, 2015

Robust 3DIC Package Assembly Process Engineering for High Volume Production

by @ 2:52 pm. Filed under ALL, Electrical/Power, Electronics Design, Semiconductors, Signal Processing
 

Wednesday, August 12, 2015 
SCV Components, Packaging, and Manufacturing Technologies (CPMT) 
Subject: Robust 3DIC Package Assembly Process Engineering for High Volume Production 
– FPGA, CoWoS (Chip-On-Wafer-On-Substrate), low power and latency, manufacturing complexity …
Speaker: Inderjit Singh, Xilinx Inc. 
Time: 11:30 am, check-in, light food, networking; 12 noon: presentation 
Cost: $5 non-IEEE members, Free for members (please use code IEEE2015); Talk-Only: Free 
Talk-Only attendees: please check-in by 11:45 
Location: Biltmore Hotel (a change from our usual TI location), 2151 Laurelwood Road (at 101), Santa Clara
Event Details: http://www.cpmt.org/scv/meetings/cpmt1508l.html 
RSVP: http://www.eventbrite.com/e/robust-3d-ic-package-assembly-process-engineering-for-high-volume-production-registration-17421205294

20150812ALL

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