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August 26, 2008

Mtg: Development and Challenges on Reliability Characterization of CMOS Devices with Gate Oxide in the Tunneling Regime

by @ 1:23 pm. Filed under ALL, NanoEngineering, Semiconductors
 

THURSDAY August 28, 2008
SCV Electron Devices? Chapter
Speaker: Dr. Steve S. Chung, National Chiao Tung University, Taiwan
Time: 6:00 PM – Pizza, 6:15 PM – Lecture
Cost: none
Place: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

Conventional CV method has been used for almost over 4 decades, in which it needs a large area capacitor for the measurement and has faced difficulties when gate leakage current exists. Several other gate oxide reliability analysis techniques, such as CP (Charge-Pumping), GD (Gated-Diode), DCIV etc. have been elaborated for similar purpose. However, as device gate oxide thickness keeps shrinking to the direct-tunneling regime (e.g., <20A), it reaches a limit for the measurement as a result of direct tunneling gate leakage and the quantum mechanical effect. This talk will give an overview of previous and the current measuring techniques for the process and reliability characterization to state-of-the-art CMOS devices. Its potential use for the device hot carrier reliability study, NBTI, and process characterization, e.g., oxide quality monitor, interface profiling, HC stress effect etc., will be presented. More recent developments for 1nm range ultra-thin gate oxide CMOS device applications will also be demonstrated. In particular, more recent applications to the reliability study of strained-silicon CMOS devices will be described. Further development and the road blocks of these techniques will be addressed.

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