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September 8, 2008

Mtg: High Performance Digital Fractional-N Frequency Synthesizers

by @ 4:26 pm. Filed under ALL, Communications, Electronics Design, Engineering Mgmt, Semiconductors
 

THURSDAY October 16, 2008
SCV Solid State Circuits Chapter
Speaker: Prof. Michael H. Perrott, MIT
Time: Refreshments at 6:00 PM; Presentation at 6:30 PM
Cost: small donation for food
Place: National Semiconductor, Building E Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/ssc

Digital phase-locked loops provide many implementation advantages compared to their analog counterparts by avoiding large capacitors for loop filters and the complications of designing analog-intensive components such as charge pumps. ? A key question, however, is whether such digital structures can support high performance applications in which low jitter and high PLL bandwidth is required? ? In this talk, we address this question by discussing techniques to achieve high performance digital fractional-N synthesizers, including high resolution time-to-digital conversion, digital quantization noise cancellation, and low-jitter divider structures. Measured results of a prototype will demonstrate that < 300 fs of rm jitter can be achieved with a relatively high PLL bandwidth of 500 kHz.

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