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July 30, 2007

8/16: A Digitally Modulated Polar CMOS PA with 20MHz Signal BW

by @ 11:52 am. Filed under ALL, Communications, Electronics Design, Semiconductors
 

THURSDAY August 16
SCV Solid State Circuits
Speaker: Amirpouya Kavousian, Stanford University
Time: Food and drinks at 6:00 PM; Presentation at 6:30 PM
Cost: Donation requested to partially cover food cost
Place: National Semiconductor Building E Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: by email through ssc_scv_rsvp@yahoogroups.com
Web: www.ewh.ieee.org/r6/scv/ssc

The advent of high-bandwidth, highly spectral-efficient communication systems, such as IEEE 802.11g, has imposed tremendous challenges on power amplifier design. Since power amplifiers are often the most power-consuming block in a wireless system, their efficiency can have a determining impact on the battery lifetime of a system. However, the high linearity required of current and emerging wireless systems has typically mandated the use of highly linear low-efficiency traditional class-A designs. This talk presents a CMOS RF power amplifier that employs a digital polar architecture to improve the overall power efficiency while providing the linearity required of IEEE 802.11g systems. An experimental prototype of the polar power m CMOS technology, occupies a total dieµamplifier, integrated in am area of 0.18 x 1.8 mm2, operates at 1.6GHz and achieves 6.7% PAE with -26.8dB EVM while delivering 13.6dBm linear output power.

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