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May 1, 2016

Designing with FinFETs

by Editor @ 2:09 pm. Filed under ALL, Reliability, Semiconductors, Signal Processing
 

Tuesday, May 10, 2016
SCV Electron Device Society (EDS)
Subject: Designing with FinFETs
-multigate transistor, microprocessor product at 22nm node, Fin formation, metrology, device parasitics, performance as well as design challenges for logic and SRAM circuits …
Speaker: Dr. Witold (Witek) P. Maszara, Distinguished Member of Technical Staff, Global Foundries
Time: 6:00 pm: Networking and refreshments; 6:15 pm to 7:00 pm: Presentation
Cost: Free
Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr., Santa Clara
Event Details: http://sites.ieee.org/scv-eds/

20160510ALL

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