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June 3, 2016

Increased Power Density and Simplified Designs with 3-D SiP Module

by @ 11:24 am. Filed under ALL, Electrical/Power, Semiconductors
 

Thursday, July 28, 2016
SCV Components, Packaging, and Manufacturing Technologies (CPMT) and SFBAC Power Electronics Society (PELS)
Subject: Increased Power Density and Simplified Designs with 3-D SiP Module
– volumetric co-design methodology and packaging construction trade-offs, SiP eco-system, co-design, construction, materials and circuit topology…
Speaker: Jim Moss, Products Technology Manager, TI
Time: 11:30 am to 12:00 noon: Registration, lunch, and networking: 12:00 to 1:00 pm: Presentation
Cost: $5 for IEEE Members, students, and retired, $10 for non-members
Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Dr., Santa Clara
Event Details: http://www.cpmt.org/scv/

20160728ALL

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