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October 15, 2008

Mtg: Spice Model Extraction for Partially-Depleted SOI Technologies in Concurrent Designs

by @ 3:23 pm. Filed under ALL, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

TUESDAY November 11, 2008
SCV Electron Devices Chapter
Speaker: Dr. Brian Chen, Synopsis
Time: Social/food at 6:15 PM; Presentation at 6:30 PM
Cost: none
Place: National Semiconductor, Building E-1, Conference Center, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

Spice model extraction for partially-depleted (PD) silicon-on-insulator (SOI) technologies needs to address a number of technical challenges on top of those encountered in conventional bulk CMOS.? They include the self-heating effect, characterization and modeling of the floating-body voltage, and its related circuit-level model validation.? Model extraction is further complicated by the necessity to support concurrent designs when little or very limited silicon (hardware) data is available.? This talk will provide a brief overview of PD SOI Spice model extraction with examples of several 90nm and 65nm case studies from various stages of model extraction, including data analysis, device-level model validation, and circuit-level model validation.

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