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November 14, 2016

Wafer Level Process Formation of a Polymer Isolated Chip Scale Package 

by @ 1:03 pm. Filed under ALL, Semiconductors
 

Tuesday, November 22, 2016 
SCV Components, Packaging, and Manufacturing Technologies (CPMT) 
Subject: Wafer Level Process Formation of a Polymer Isolated Chip Scale Package 
– After reflow, this excess solder may cause a high leakage path or short, silicon sidewalls and backside are completely covered by a thin non-conducting polymer material, polymer isolated CSP solution… 
Speaker: Harry Gee, Device Engineer, On Semiconductor 
Time: 11:30 am: Registration, networking, sandwiches/drinks; 12:00 pm: Presentation. Presentation-only: please arrive at 11:45 am to register in advance of beginning of talk. Cost: IEEE Member, students, unemployed: $5; non-IEEE Member: $10; 
Location: Texas Instruments, 2900 Semiconductor Way, Bldg. E Auditorium, Santa Clara 
– Event Details: http://www.cpmt.org/scv/ 

20161122ALL

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