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November 16, 2017

10th MOS-AK Compact Modeling Workshop in the Silicon Valley

by @ 7:20 pm. Filed under ALL, Electronics Design
 

Wednesday, December 6, 2017 
SFBA Electron Devices Society (EDS) 
Subject: 10th MOS-AK Compact Modeling Workshop in the Silicon Valley
– frontiers of the compact modeling for nm-scale MEMS designs and CMOS/SOI circuit simulations, compact/SPICE modeling and its Verilog-A standardization, physical, analytical and numerical models… 
Speaker: Wladek Grabinski 
Time: 
Cost: 
Location: Cadence Design Systems, 2655 Seely Ave, Building 5, San Jose 
Event Details: http://www.mos-ak.org/silicon_valley_2017 

20171206ALL

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