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January 29, 2009

Mtg: High Performance, Low Power I/O for Chip-to-chip Communications

by @ 2:21 pm. Filed under ALL, Communications, Computers/Software, Electronics Design, Semiconductors
 

WEDNESDAY March 11, 2009
SCV Components, Packaging & Manufacturing Technology Chapter
Speaker: Dr. Christopher Sellathamby, Vice President, Scanimetrics
Time: Optional dinner at 6:30 PM; Presentation at 7:30 PM
Cost: $25 if reserved by March 9; $30 at door (no cost for presentation)
Place: Biltmore Hotel, 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara
RSVP: via the DoubleKnot registration page, from website
Web: www.cpmt.org/scv

The continued demand for smaller microchips and better performance has created a crisis in interconnectivity between chips รข?? input/output (I/O) data throughput is a bottleneck in high-speed chip-to-chip communication.? This presentation discusses the latest technical innovations for increasing bandwidth and transmission distance while reducing power consumption and silicon area.? Techniques which can be integrated into current testing, manufacturing and packaging technologies with minimal changes to existing production infrastructure are a priority.? ? Solutions discussed in this presentation are based on inductive coupling methodologies to meet requirements of the semiconductor industry roadmaps, including 3D and SiP applications.

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