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September 30, 2007

Mtg: 450mm Wafers: What will it Cost to Get There?

by @ 10:11 am. Filed under ALL, Electronics Design, Engineering Mgmt, NanoEngineering, Semiconductors
 

TUESDAY November 13
SCV Electron Devices Chapter
Speaker: Dan Hutcheson, VLSI Research Inc.
Time: Social at 6:00 PM, Presentation: 6:15 PM
Cost: none
Place: National Semiconductor Corp. Building E-1 – Auditorium CMA, 2900 Semiconductor Drive, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

Tensions are high as the industry confronts the issue of 450mm. Some believe it is absolutely necessary. It was scheduled in the ITRS roadmap to be ready by 2012 and believed essential to keep chip makers on Moore’s cost/performance curve. Now it’s been pushed out to 2015. Meanwhile, with 300mm just past the toddler stage, others believe 450mm will be a disaster and are fighting tooth and nail behind the scenes to stop it. Today, they represent the majority. It’s not just the equipment makers who are in this camp. It is also the majority of chip makers. Many believe Moore‘s law must slow; that staying on it is unaffordable; that 450mm will lead to even worse scale problems than 300mm; and that if it happens the result will be more consolidation and even harder times.

In favor of the people arguing for it is the fact that every wafer size jump has met with resistance based on the same reasoning. But there are reasons to believe that this time things will be different. The industry’s growth has slowed. Plus, 300mm proved to be incredibly painful for the equipment industry. Few argue with these differences.

This talk delves deeply into the history of wafer size transitions, examining their costs and benefits. It then examines alternative scenarios for 450mm. It is based on Dan’s Chip Insider® articles.

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