IEEE S.F. Bay Area Council e-GRID's

Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences

March 1, 2009

Mtg: The Multi-Dimensional Design Space of Power, Reliability, Temperature and Voltage in Highly Scaled Geometries

by @ 4:06 pm. Filed under ALL, Communications, Computers/Software, NanoEngineering, Semiconductors

MONDAY March 2, 2009
SCV Circuits and Systems Chapter
Speaker: Fadi Kurdahi, Department of Electrical Engineering and Computer Science, UC-Irvine
Time: Networking & fast food at 6:30 PM; Presentation at 7:00 PM
Cost: none
Place: Cadence Design Systems, Building 5, 655 Seely Avenue, San Jose
RSVP: not required

Increased operating temperatures of chips have aggravated leakage and reliability issues, both of which are adversely affected by high temperature. Due to thermal diffusion among IP-blocks and the interdependence of temperature and leakage power, we observe that the floor-plan has an impact on both the temperatures and the leakage of the IP-blocks in a System on Chip (SoC).? An increase in temperature also increases the probability of errors such as read/write errors or unstable memory accesses. We show that contrary to conventional wisdom, increasing the supply voltage on an SRAM to guarantee stability, might lead to the exact opposite by increasing the probability of error due to temperate increase.? Thus supply voltage, power, temperature, and probability of errors influence each other mutually and must be considered during robust circuit design. We will discuss approaches for fast and efficient design space exploration that account for dynamic and leakage power as well as the impact of voltage scaling, floor-planning and temperature gradients across the system on a chip.? Furthermore, we will present recent results obtained from applying our floor-planner on eight industrial SoC designs from Freescale Semiconductor Inc. where we observed up to 135% difference in the leakage power between leakage-unaware and leakage aware floor-planning. We will also demonstrate designs where thermal aware floor planning can reduce the total power dissipation by up to 50%.

Comments are closed.

[IEEE S.F. Bay Area Council -] [powered by WordPress .]

SF Bay Area Council


  • 5G (2)
  • ALL (4,702)
  • Antennas & Propagation (5)
  • BioEngineering (675)
  • Blogroll (33)
  • Circuits (16)
  • Communications (1,862)
  • Computers/Software (1,777)
  • Consumer Electronics (103)
  • Control Systems (23)
  • Electrical/Power (1,284)
  • Electronics Design (2,774)
  • Employment (4)
  • Employment opportunities (7)
  • Engineering Mgmt (1,819)
  • Green energy (48)
  • History (7)
  • Industrial Applications (91)
  • Information Theory (13)
  • Instrument and Measurement (1)
  • Magnetics (30)
  • Microwave (8)
  • NanoEngineering (876)
  • Optics/Displays (969)
  • Photonics (31)
  • PhotoVoltaics (4)
  • Product Safety (25)
  • Reliability (37)
  • Robotics and Automation (19)
  • Semiconductors (1,847)
  • Signal Processing (138)
  • Vehicular Technology (16)
  • Women in Engineering (8)
  • Young Professionals (5)

    Support our advertisers:

    Visit our

    Enabling Javascript allows us to show you upcoming conferences in this column.

    For the Firefox browser, select Tools/Options/Content and select "Enable Javascript".

    If you are using Microsoft Internet Explorer you may need to click on the yellow bar above and select 'Allow Blocked Content'. You must then click 'Yes' on the following security warning.


    November 2019
    S M T W T F S
    « May    

    View in Google Calendar

    search blog:

    SUBSCRIBE: Get the e-GRID twice a month by email - upcoming IEEE SF Bay Area meetings, conferences.

    RSS Feed Subscribe to our RSS Feed.

    PUBLICIZE your event to IEEE's membership.

    general links:

    22 queries. 0.340 seconds